A ferroelectric memory is a nonvolatile semiconductor memory having the same memory cell structure as a DRAM (Dynamic Random Access Memory) but using a ferroelectric capacitor (ferroelectric element) in a part corresponding to a dielectric capacitor in a memory cell of the DRAM. As a memory cell (storage unit of one bit data) of the ferroelectric memory, there are one transistor/one capacitor (1T/1C) type cell and two transistors/two capacitors (2T/2C) type cell, as disclosed in Japanese Patent Application Laid-open No. Hei 5-89692.
The ferroelectric memory stores binary data of “1”, “0” by associating them with two different polarization states of the ferroelectric capacitor, and the memory cell exhibits nonvolatility when retaining data. However, reading out of data from the memory cell is destructive reading, which destroys and erases the retained data. Accordingly, in a reading sequence of data, a so-called restore operation (rewrite operation) is performed such that after a minute potential which appears on a bit line according to the retained data is amplified by a sense amplifier to obtain reading data as digital information, the data is written back to the memory cell.
Here, the conventional ferroelectric memory temporarily stores data read out from the memory cell by an electrical signal level (high level or low level) on the bit line until it performs the restore operation in the reading sequence of data, and thus it has instability in a retaining state of data. In other words, the conventional ferroelectric memory retains data read out from the memory cell by a volatile electric charge, and therefore it has possibility of losing data due to a power cut-off (including a cut-off of power supply, decrease of a power supply voltage), noise interference, swing of potential, and the like.
In the conventional ferroelectric memory, when the reading sequence of data is started, an externally inputted control signal and the like are controlled inside the memory device so that the sequence is not interfered from the outside until the restore operation is completed, in order to guarantee writing of data by the restore operation. Furthermore, in the conventional ferroelectric memory, a capacitor and so on for power supply for assuring stable power supply until the reading sequence is completed are provided internally, thereby causing enlargement of circuit area (chip area). According to the means as described above, data read out from the memory cell during the read sequence can be almost securely written (written back) to the memory cell, but it is not possible to confirm whether the reading sequence of data including the restore operation is completed properly or not.
Further, for the conventional ferroelectric memory, there has been a method using a so-called shadow RAM (a memory incorporating a pair of memory cells having the same data), and if data stored in a reading memory (one memory) is destroyed, the data is guaranteed by data stored in the other memory. However, since this method stores the same data in two areas, it needs a memory having storage capacity that is at least double of the amount of data, and its operation is complicated because data has to be synchronized constantly between the pair of memories.
Patent Document 1
Japanese Patent Application Laid-open No. Hei 5-89692